Recently, there has been a high demand for downscaling semiconductor storage devices such as a NAND flash memory (NAND EEPROM). However, when such a memory is downscaled, a space between memory cells is reduced and thus interference between the memory cells (adjacent interference effect) becomes an unignorable level. The adjacent interference effect is a phenomenon that a threshold voltage of a memory cell in which data has been written is shifted by a data writing operation on an adjacent memory cell. The adjacent interference effect enlarges distribution of the threshold voltage of the memory cell and thus the reliability of read data is degraded.
The adjacent interference effect is caused by a large coupling capacitance between adjacent memory cells. Accordingly, in order to reduce the coupling capacitance between adjacent memory cells, it is conceivable to have an air gap with a reduced dielectric constant formed between memory cells. Furthermore, in order to reduce an adjacent interference effect between a memory cell and a selective transistor, it is conceivable to have an air gap also formed between the memory cell and the selective transistor.
However, when an air gap is formed between adjacent memory cells and between a memory cell and a selective transistor, the air gap is formed also between the selective transistor and a contact and between a transistor of a peripheral circuit and the contact. In this case, a contact hole formed in the vicinity of the selective transistor and the transistor of the peripheral circuit communicates with the air gap, in such a manner that a material for a contact enters into the air gap. This phenomenon leads to a short-circuit between contacts adjacent to each other in a bit line direction. This also reduces a breakdown voltage between the selective transistor and the contact and causes deterioration in the reliability of the memory.
To handle these problems, the contact hole needs to be formed to be further away than the air gap in such a manner that the contact hole does not communicate with the air gap. In this case, the space between the transistor and the contact and the space between transistors in the peripheral circuit need to be designed to be wide. This arrangement prevents downscaling of memories.